module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

    parameter IDLE = 2'd0;
    parameter F_ONE = 2'd1;
    parameter ZERO = 2'd2;
    parameter ONE = 2'd3;
    
    reg	[1:0]	state;
    reg	[1:0]	next_state;
    
    always @(posedge clk or posedge areset)
        begin
            if(areset)
                begin
                    state <= IDLE;
                end
            else
                begin
                    state <= next_state;
                end
        end
    
    always @(*)
        begin
            case(state)
                IDLE:	next_state = x ? F_ONE : IDLE;
                F_ONE:	next_state = x ? ONE : ZERO;
                ZERO:	next_state = x ? ONE : ZERO;
                ONE:	next_state = x ? ONE : ZERO;
            endcase
        end
    
    assign z = (state == ZERO) || (state == F_ONE);
    
endmodule
